Kurs/Prototyping med FPGA

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Revision as of 10:47, 26 October 2010 by Oysteini (talk | contribs) (Stedet er R9)
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Tid: Torsdag 4. november 2010, kl. 18:15
Sted: R9
Kursholder: Odd Rune S. Lykkebø

The course will take a stab at explaining the common basics of commercial FPGAs. We will then demonstrate the basics of hardware design languages (HDL) and present an example of prototyping a design in FPGA where we go slightly in-depth about the tools used and the results they produce. We will also touch briefly on the subject of achieving timing closure in high-speed designs.

The course is aimed at people interested in hardware. If you know the difference between a mealy and moore state machine (or know that there *is* a difference).