Difference between revisions of "Kurs/Prototyping med FPGA"

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<b>Kursholder</b>: Odd Rune S. Lykkebø
 
<b>Kursholder</b>: Odd Rune S. Lykkebø
  
(Mer informasjon kommer etter hvert).
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The course will take a stab at explaining the common basics of commercial FPGAs. We will then demonstrate the basics of hardware design languages (HDL) and present an example of prototyping a design in FPGA where we go slightly in-depth about the tools used and the results they produce. We will also touch briefly on the subject of achieving timing closure in high-speed designs.

Revision as of 10:03, 19 October 2010

Tid: Torsdag 4. november 2010, kl. 18:15
Sted: Annonseres senere
Kursholder: Odd Rune S. Lykkebø

The course will take a stab at explaining the common basics of commercial FPGAs. We will then demonstrate the basics of hardware design languages (HDL) and present an example of prototyping a design in FPGA where we go slightly in-depth about the tools used and the results they produce. We will also touch briefly on the subject of achieving timing closure in high-speed designs.